1. Field of the Invention
The present invention relates to a clock reproduction circuit and a data transmission apparatus which can be applied to a serial data transmission apparatus etc. for transmitting serial data at a high speed.
2. Description of the Related Art
Serial data transmission enables transmission of signals by one or a pair of transmission media, therefore is excellent in space saving and does not suffer from the problem of skew (timing deviation) between data occurring when transmitting signals by a signal transmission line having many cores, therefore is suited to long distance data transmission.
FIG. 5 shows a configuration of a general serial data transmission apparatus. The illustrated data transmission apparatus is constituted by a transmission unit 10, a transmission line 20, and a reception unit 30. Further, the transmission unit 10 comprises a parallel/serial conversion circuit 11 and a transmission clock generation circuit 12, while the reception unit 30 comprises a serial/parallel conversion circuit 31 and a clock reproduction circuit 32.
Further, the transmission line 20 is constituted by a pair of signal lines, for example, a shielded twisted pair (STP) or unshielded twisted pair (UTP).
At the time of data transmission, for example, n bits of transmission data input to the transmission unit 10 are converted to serial data in synchronization with a transmission clock signal TCK by the parallel/serial conversion circuit 11 and then output to the transmission line 20.
The transmission clock generation circuit 12 is constituted by for example a PLL circuit, receives a synchronization clock signal CLK, generates a transmission clock signal TCK in accordance with this, and outputs the same to the parallel/serial conversion circuit 11.
The reception unit 30 receives the serial data transmitted through the transmission line 20, converts this to n bits of data by the serial/parallel conversion circuit 31, and then output the same.
The clock reproduction circuit 32 is constituted by for example a PLL circuit, reproduces a reception use clock signal LCK having the same frequency as that of the transmission clock signal TCK based on the transmission data of the transmission line 20, and supplies the same to the serial/parallel conversion circuit.
By the above data transmission apparatus, the transmission data can be transmitted at a high speed by for example a pair of transmission lines, so there is excellent space saving of transmission line. Further, data transmission over a long distance with little distortion of data can be realized.
The data transmission apparatus of the above-mentioned related art has the problem that a circuit for extracting the clock signal from the transmission data per se, that is, the clock reproduction circuit 32, is indispensable for the reception unit 30 to correctly receive the data transmitted from the transmission unit 10.
The clock reproduction circuit 32 can be constituted by a band pass filter having a high Q value or a PLL circuit.
When the clock reproduction circuit 32 is constituted by a band pass filter, generally the differential waveform of the received signal is filtered by a surface acoustic wave (SAW) filter or the like to extract the clock signal. In this method, there is the limitation that this cannot be applied to a transmission rate other than the center frequency of the SAW filter.
When the clock reproduction circuit 32 is constituted by the PLL circuit, control is performed so that the phase of the received signal and the phase of the output of a voltage-controlled oscillator (VCO) become equal and the clock signal is extracted. In this method, there is an advantage that it is possible to handle a variety of data transmission rates if a wide oscillation frequency range of the VCO is taken.
However, when the frequency of the VCO deviates by a large extent from the frequency of the received signal, a phase comparing means, which assumes serial data signals of a random bit train, becomes confused, the VCO drifts in state or becomes locked to a frequency of a whole multiple of the transmission rate, and the transmission clock signal TCK sometimes cannot be correctly extracted.
One method of solving the above problem, is adopted of applying a reference clock signal having a frequency of a specific ratio relative to the rate of the signal to be transmitted to the reception unit 30 and locking the PLL circuit in an initialized state of the reception unit 30. Using this method, however, when the transmission rate of the serial data transmitted by the transmitter is not known, the frequency of the reference clock signal cannot be set, therefore another means of transmitting information concerning the transmission rate becomes necessary.